The present invention relates to a PLL circuit, and more particularly, to a PLL circuit using a sigma-delta modulator.
In recent years, PLL circuits for use in mobile communication devices, such as cellular phones, are required not only to be further highly integrated and consume less power but must also improve their channel switching speed and C/N (carrier-to-noise ratio) characteristic. To satisfy these requirements, PLL circuits using sigma-delta modulators have been commercialized. The PLL circuits using sigma-delta modulators are required to further improve their channel switching speed and C/N characteristic.
The channel switching time and the C/N characteristic are loop characteristics that are important in PLL circuits. More specifically, a PLL circuit is required to shorten the time taken to switch from one lockup frequency to another lockup frequency, while reducing phase noise contained in the frequency of an output signal.
To satisfy these requirements, a fractional-N PLL frequency synthesizer (PLL circuits) has been commercialized in recent years. The fractional-N PLL frequency synthesizer uses a fractional frequency division ratio of a comparator/frequency divider that forms a PLL loop. Such a fractional frequency division type PLL circuit increases the frequency of a reference signal and is thus advantageous in improving the channel switching time and the C/N characteristic.
However, the fractional value for the fractional frequency division ratio is obtained in an equivalent and averaged manner by changing the integral frequency division value over time. More specifically, the fractional frequency division ratio is obtained in an equivalent manner by cyclically performing frequency division by N+1 while constantly performing frequency division by a fixed frequency division value N. For example, for a frequency division of 1/8, the eight frequency division operations are performed by repeating N frequency division seven times and N+1 frequency division once. In the frequency division of 3/8, eight frequency division operations are performed by repeating N frequency division five times and N+1 frequency division three times.
However, when using a phase comparator to compare the comparison signal obtained from the fractional frequency division operation with a reference signal, the N frequency division and N+1 frequency division are cyclically repeated. This results in a cyclic phase error. As a result, spurious noise is generated in the output signal of a voltage controlled oscillator.
As one method for preventing generation of such spurious noise resulting from fractional frequency division, a sigma-delta fractional-N PLL frequency synthesizer 100 including a multi-stage noise shaping (MASH) sigma-delta modulator, as shown in FIG. 13, has been proposed. The sigma-delta modulator provides one method for randomly changing the frequency division value that is used in fractional frequency division to prevent generation of spurious noise.
In FIG. 13, an oscillator 1 outputs a reference clock signal, which has an inherent frequency based on the oscillation of a crystal oscillator, to a reference frequency divider 2. The reference frequency divider 2, which is formed by a counter circuit, outputs a reference signal fr, which is generated by dividing the frequency of the reference clock signal based on a preset frequency division ratio, to a phase comparator 3.
A comparison signal fp is input into the phase comparator 3 from a comparator/frequency divider 4. The phase comparator 3 outputs a pulse signal, which is in accordance with the phase difference between the reference signal fr and the comparison signal fp, to a charge pump 5.
The charge pump 5 outputs an output signal to a lowpass filter (LPF) 6 based on the pulse signal output from the phase comparator 3.
This output signal is formed by a direct current element containing a pulse element. The direct current element changes as the frequency of the pulse signal changes. The pulse element changes based on the phase difference of the pulse signal.
The LPF 6 outputs, as a control voltage, an output signal, which is obtained by smoothing the output signal of the charge pump 5 and removing high frequency elements from the smoothed signal, to a voltage controlled oscillator (VCO) 7.
The VCO 7 outputs an output signal fvco, which has frequency that is in accordance with the control voltage, to an external circuit and the comparator/frequency divider 4.
The frequency division ratio of the comparator/frequency divider 4 is set in a manner that the ratio is freely changed by a sigma-delta modulator 8.
The sigma-delta modulator 8 is formed as a third-order modulator including integrators (Σ) 9a to 9c having n bits, differentiators (Δ) 10a to 10f formed by flip-flop circuits, and an adder 11. The integrators 9a to 9c and the differentiators 10a to 10f operate using the comparison signal fp input from the comparator/frequency divider 4 as a clock signal.
A numerator value F of the sigma-delta modulator 8 is input into the integrator 9a from an external device (not shown). The integrator 9a accumulates the input value F based on a clock signal. When the accumulated value exceeds a denominator value (modulo value) Q, the integrator 9a outputs an overflow signal OF1. After the overflow, the integrator 9a divides the accumulated value by the denominator value Q, and continues accumulating the input value F.
The denominator value (modulo value) Q is set at 2n. The numerator value F is input as a digital signal having n−1 bits with respect to the power n of the denominator value Q. The denominator value Q, which is the same value for the integrators 9a to 9c, is, for example, 1024, and the numerator value F is 30.
The overflow signal OF1 of the integrator 9a is provided as an input signal a to the adder 11 via the differentiators 10a and 10b. An accumulated value X1 of the integrator 9a is provided to the integrator 9b. 
The integrator 9b, which performs an accumulating operation of an input signal having the accumulated value X1, outputs an accumulated value X2 resulting from the accumulation to the integrator 9c. Further, an overflow signal OF2 output from the integrator 9b is provided as an input signal b to the adder 11 via the integrator 10c and as an input signal c to the adder 11 via the differentiators 10c and 10d. 
The integrator 9c, which performs an accumulating operation of an input signal having the accumulated value X2, outputs an overflow signal OF3. The overflow signal OF3 is provided as an input signal d to the adder 11, provided as an input signal e to the adder 11 via the integrator 10e, and provided as an input signal f to the adder 11 via the differentiators 10e and 10f. 
The differentiators 10a, 10b, and 10d are included to correct errors in the timings of the input signals a to f that may be caused by the operations of the differentiators 10c, 10e, and 10f in accordance with the clock signal.
Based on the input signals a to f, the adder 11 performs the computation:(+1)a+(+1)b+(−1)c+(+1)d+(−2)e+(+1)f.
The coefficients by which the input signals a to f are multiplied are set based on Pascal's triangle.
FIG. 7 shows the computation result (excluding +N) of the computation operation performed by the adder 11 described above. As shown in the drawing, the adder 11 generates random numbers that change arbitrarily in a range of +4 to −2.
A fixed frequency division ratio N that is set in advance is input into the adder 11. The adder 11 adds the above computation result to the fixed frequency division ratio N and outputs the result to the comparator/frequency divider 4.
With this operation performed by the adder 11, the frequency division ratio input into the comparator/frequency divider 4 changes randomly with respect to the fixed frequency division ratio N in a manner such as N, N+1, N, N−2, N+3, N−1, . . . , N+4, to N−1.
In the comparator/frequency divider 4, a fractional frequency division operation is performed averagely based on the frequency division ratio output from the adder 11.
FIG. 7 shows examples of the random numbers that are the computation values output from the adder 11 of the third-order sigma-delta modulator 8 shown in FIG. 13. FIG. 10 shows examples of random numbers generated in a second-order sigma-delta modulator. As shown in the two drawings, the fluctuation width of the output signal of the sigma-delta modulator increases and the modulation width of the frequency division ratio of the comparator/frequency divider 4 increases as the order number of the sigma-delta modulator increases.
FIG. 15 shows the frequency spectrum of the output signal of the fractional-N PLL frequency synthesizer 100 using the third-order sigma-delta modulator described above. FIG. 14 shows the frequency spectrum of the output signal of a fractional-N PLL frequency synthesizer using a second-order sigma-delta modulator, and FIG. 16 shows the same frequency spectrum in the case of a fourth-order sigma-delta modulator.
As apparent when comparing FIGS. 14 to 16, the noise level in the lockup operation of the PLL increases and the C/N characteristic is deteriorated as the order number of the sigma-delta modulator becomes higher.
The C/N characteristic is improved as the order number of the sigma-delta modulator becomes lower. However, the sigma-delta modulation is unstable in this case. Such unstable sigma-delta modulation adversely affects the output signal of the sigma-delta modulator.